Multi‐bit Sigma‐Delta Modulator for Low Distortion and High‐Speed Operation
Multi‐bit Sigma‐Delta Modulator for Low Distortion and High‐Speed Operation
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用于低失真和高速操作的多位 Sigma-Delta 调制器
DOI：
10.4218/etrij.07.0207.0140
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发表时间：
2007
期刊：
影响因子：
1.4
通讯作者：
Jong
中科院分区：
文献类型：
--
作者：
Yi;Jong
描述了一种用于低失真性能和高速运行的多位 Σ-Δ 调制器架构。所提出的架构在反馈路径中使用模数转换器的延迟码和延迟差分码，从而抑制积分器中的信号分量并放宽模数转换器和扰码器逻辑的时序要求。 Σ-Δ调制器采用0.13μm CMOS工艺实现，实现了高线性度。对于−6 dBFS 输入信号，测得的无杂散动态范围为 89.1 dB。
A multi‐bit sigma‐delta modulator architecture is described for low‐distortion performance and a high‐speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog‐to‐digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog‐to‐digital converter and the scrambler logic. Implemented by a 0.13 μm CMOS process, the sigma‐delta modulator achieves high linearity. The measured spurious‐free dynamic range is 89.1 dB for −6 dBFS input signal.