Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors
Joint application mapping/interconnect synthesis techniques for embedded chip-scale multiprocessors
复制标题
用于嵌入式芯片级多处理器的联合应用映射/互连综合技术
DOI：
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发表时间：
2005
影响因子：
5.3
通讯作者：
S. Bhattacharyya
中科院分区：
文献类型：
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作者：
N. Bambha;S. Bhattacharyya
随着晶体管尺寸的缩小，互连代表了芯片设计者越来越多的瓶颈。有几个小组正在开发新的互连方法和系统架构，以科普这一趋势。新的体系结构需要新的方法来进行高级应用映射和硬件/软件协同设计。我们提出了高层次的调度和互连拓扑合成技术的嵌入式多处理器片上系统，简化了一个或多个数字信号处理应用。也就是说，我们寻求合成一个应用程序特定的互连拓扑结构。我们表明，灵活的互连拓扑结构，利用处理器之间的低跳通信提供的优势，降低功耗和延迟。我们表明，现有的多处理器调度算法可以死锁，如果拓扑图不是强连接的，或者如果施加约束的最大数量的跳数允许通信。我们详细介绍了一个有效的算法，可以与现有的调度算法，以避免这种死锁。我们表明，这是有利的，以执行应用程序调度和互连综合联合，并提出了一个概率调度/互连算法，利用图同构帕雷设计空间。
As transistor sizes shrink, interconnects represent an increasing bottleneck for chip designers. Several groups are developing new interconnection methods and system architectures to cope with this trend. New architectures require new methods for high-level application mapping and hardware/software codesign. We present high-level scheduling and interconnect topology synthesis techniques for embedded multiprocessor systems-on-chip that are streamlined for one or more digital signal processing applications. That is, we seek to synthesize an application-specific interconnect topology. We show that flexible interconnect topologies utilizing low-hop communication between processors offer advantages for reduced power and latency. We show that existing multiprocessor scheduling algorithms can deadlock if the topology graph is not strongly connected, or if a constraint is imposed on the maximum number of hops allowed for communication. We detail an efficient algorithm that can be used in conjunction with existing scheduling algorithms for avoiding this deadlock. We show that it is advantageous to perform application scheduling and interconnect synthesis jointly, and present a probabilistic scheduling/interconnect algorithm that utilizes graph isomorphism to pare the design space.