Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model
Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model
复制标题
使用完整串扰噪声模型分析 DSM 互连中的噪声避免技术
DOI：
10.1109/date.2002.998313
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
I. Hajj
中科院分区：
文献类型：
--
作者：
M. Becer;V. Zolotov;D. Blaauw;R. Panda;I. Hajj
噪声估计和避免在当今高性能IC设计中变得至关重要，“必须具备”能力。一个精确而高效的串扰噪声模型包含尽可能多的驱动器/互连参数，对于任何基于灵敏度的噪声避免方法都是必要的。在本文中，我们提出了一个完整的分析串扰噪声模型，该模型包含了所有物理特性，包括受害者和攻击者的驱动器，互连的分布式RC特性以及受害者和攻击者线路中的耦合位置。我们给出了峰值噪声和噪声宽度以及对所有模型参数的灵敏度的封闭式解析表达式。然后，我们使用它们模型参数灵敏度来分析和评估各种噪声避免技术，如驱动器尺寸，线尺寸，线间距和层分配。我们的模型和噪声避免评估都使用0.13/spl mu/技术的实际电路进行了验证。我们还介绍了在高性能微处理器内核上讨论的噪声避免技术的有效性。
Noise estimation and avoidance are becoming critical, 'must have' capabilities in today's high performance IC design. An accurate yet efficient crosstalk noise model which contains as many driver/interconnect parameters as possible, is necessary for any sensitivity based noise avoidance approach. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width as well as sensitivities to all model parameters. We then use them model parameter sensitivities to analyze and evaluate various noise avoidance techniques such as driver sizing, wire sizing, wire spacing and layer assignment. Both our model and noise avoidance evaluations are verified using realistic circuits in 0.13/spl mu/ technology. We also present effectiveness of discussed noise avoidance techniques on a high performance microprocessor core.