Design Space Exploration for Chiplet-Assembly-Based Processors
Design Space Exploration for Chiplet-Assembly-Based Processors
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基于 Chiplet 组装的处理器的设计空间探索
DOI：
10.1109/tvlsi.2020.2968904
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发表时间：
2020
影响因子：
2.8
通讯作者：
Puneet Gupta
中科院分区：
文献类型：
--
作者：
Saptadeep Pal;Daniel Petrisko;Rakesh Kumar;Puneet Gupta
2.5-D集成技术的最新进展已经使小芯片组装成为可行的系统设计方法。小芯片组装正在以较低的成本、设计工作量和周转时间作为异构设计的新范例出现，并且实现了硬件的低成本定制。然而，这种方法的成功取决于识别提供这些益处的最小芯片集。我们开发了第一个微架构设计空间探索框架的小芯片组装为基础的处理器，使我们能够识别的最小集的小芯片设计和制造。由于小芯片组装使得异构技术和成本有效的应用相关定制成为可能，我们展示了使用由多个小芯片构建的多个系统来服务不同工作负载的好处（与单个最佳系统相比，能量延迟乘积提高了35%）以及小芯片组装方法在总成本方面优于片上系统（SoC）方法（成本最高可降低72%），同时满足个别应用的能源和性能限制。
Recent advancements in 2.5-D integration technologies have made chiplet assembly a viable system design approach. Chiplet assembly is emerging as a new paradigm for heterogeneous design at lower cost, design effort, and turnaround time and enables low-cost customization of hardware. However, the success of this approach depends on identifying a minimum chiplet set which delivers these benefits. We develop the first microarchitectural design space exploration framework for chiplet assembly-based processors which enables us to identify the minimum set of chiplets to design and manufacture. Since chiplet assembly makes heterogeneous technology and cost-effective application-dependent customization possible, we show the benefits of using multiple systems built from multiple chiplets to service diverse workloads (up to 35% improvement in energy-delay product over a single best system) and advantages of chiplet assembly approaches over system-on-chip (SoC) methodology in terms of total cost (up to 72% improvement in cost) while satisfying the energy and performance constraints of individual applications.