Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging
Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging
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DOI：
10.1007/s00170-021-08622-x
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发表时间：
2022-01
期刊：
影响因子：
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通讯作者：
F. Inoue;A. Phommahaxay;Yohei Gokita;Berthold Möller;E. Beyne
中科院分区：
文献类型：
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作者：
F. Inoue;A. Phommahaxay;Yohei Gokita;Berthold Möller;E. Beyne
我们使用平面刨床工艺来最小化由未优化的铜柱和硅薄化工艺引起的模内和晶圆内不均匀性。在300mm晶圆中，平面化铜柱的高度变化是晶圆内均匀度的3.5%，这表明电沉积后的高度变化大大减少。此外，表面刨削处理后的铜柱表面形貌平整均匀。背景研磨带层合铜柱晶片的总厚度变化为31.77µm。通过平面刨床工艺，这一变化减小到14.55µm。通过研磨，将带平磨带的Cu柱晶圆体Si减薄至100µm。背景带经过表面刨削加工后，Si的总厚度变化为1.52µm，而未经过表面刨削加工的情况下，Si的总厚度变化为8.2µm。这些结果表明，平面刨床工艺是实现高共面性的一种有前途的方法，从而代表着向高成品率先进封装的进步。
We used the surface planer process to minimize the within-die and within-wafer nonuniformity caused by the nonoptimized Cu pillar and Si thinning processes. The height variation of the planarized Cu pillars was 3.5% of the within-wafer uniformity in a 300-mm wafer, which represents a substantial reduction of the post-electrodeposition height variation. In addition, the topography of the Cu pillar surface was flat and uniform after the surface planer process. The backgrind tape-laminated Cu pillar wafer exhibited a total thickness variation of 31.77 µm. This variation was reduced to 14.55 µm by the surface planer process. The bulk Si of the Cu pillar wafer with the planarized backgrind tape was thinned to 100 µm by grinding. The total thickness variation of the Si was 1.52 µm when the backgrind tape was subjected to the surface planer process, whereas it was 8.2 µm in the case where the surface planer process was not applied. These results indicate that the surface planer process is a promising method for achieving high coplanarity of a die and wafer, thereby representing an advancement toward high-yield advanced packaging.