An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture
An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture
复制标题
基于 FPGA 的高效并行相位展开硬件架构
DOI：
10.1109/tci.2017.2663767
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发表时间：
2017
影响因子：
5.4
通讯作者：
Chau
中科院分区：
文献类型：
--
作者：
Huan;S. Hsu;Wen;Chau
本文提出了一种用于成像应用的新颖的相位展开硬件架构。该架构是基于最小均方算法的路径无关非迭代离散余弦变换 (DCT) 的硬件实现，可实现准确、快速的相位展开。该实现基于现场可编程门阵列。该架构能够利用算法不同阶段之间的并行性来最大化计算的吞吐量。为计算时间测量构建了片上网络平台。与其他快速相位展开的实现相比，所提出的架构具有高吞吐量、高精度和低功耗的优点。
This paper presents a novel phase unwrapping hardware architecture for imaging applications. The architecture is a hardware implementation of a path-independent noniterative discrete cosine transform (DCT) based minimum mean square algorithm for accurate and fast phase unwrapping. The implementation is based on field programmable gate array. The architecture is able to exploit the parallelism among different stages of the algorithm for maximizing the throughput of the computation. A network-on-chip platform is built for the computation time measurement. As compared with other implementations for fast phase unwrapping, the proposed architecture has the advantages of high throughput, high accuracy, and low power consumption.