Modular Hardware Design with Timeline Types

Modular Hardware Design with Timeline Types
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具有时间线类型的模块化硬件设计

DOI:
10.1145/3591234
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发表时间:
2023
影响因子:
--
通讯作者:
Sampson, Adrian
Sampson, Adrian
中科院分区:
--
文献类型:
--
作者:
Nigam, Rachit;Azevedo de Amorim, Pedro Henrique;Sampson, Adrian

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模块化设计是实现硬件模块大规模重用的关键挑战。然而,与软件不同的是,硬件设计与物理电路相对应,并从物理电路继承约束。定时约束(信号到达哪个周期、何时读取输入)和结构约束(乘法器接受新输入的频率)是硬件接口的基础。现有的硬件设计语言不提供一种方法来编码这些约束,用户必须阅读文档,构建脚本,或在最坏的情况下,一个模块的实现,以了解如何使用it.We提出的灯丝,一种语言的模块化硬件设计,支持规范和执行的时间和结构约束静态调度管道。灯丝使用estimeline类型,描述给定信号可用或需要时的时钟周期时间间隔。Filament支持硬件模块的安全组合,确保最终设计正确流水线化,并可预见地将其降低为高效硬件。
Modular design is a key challenge for enabling large-scale reuse of hardware modules. Unlike software, however, hardware designs correspond to physical circuits and inherit constraints from them. Timing constraints—which cycle a signal arrives, when an input is read—and structural constraints—how often a multiplier accepts new inputs—are fundamental to hardware interfaces. Existing hardware design languages do not provide a way to encode these constraints; a user must read documentation, build scripts, or in the worst case, a module’s implementation to understand how to use it. We present Filament, a language for modular hardware design that supports the specification and enforcement of timing and structural constraints for statically scheduled pipelines. Filament usestimeline types, which describe the intervals of clock-cycle time when a given signal is available or required. Filament enablessafe compositionof hardware modules, ensures that the resulting designs are correctly pipelined, and predictably lowers them to efficient hardware.
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