High-Level Synthesis with Timing-Sensitive Information Flow Enforcement
High-Level Synthesis with Timing-Sensitive Information Flow Enforcement
复制标题
DOI：
10.1145/3240765.3243415
复制
发表时间：
2018-11
期刊：
影响因子：
--
通讯作者：
Zhenghong Jiang;Steve Dai;G. E. Suh;Zhiru Zhang
中科院分区：
文献类型：
--
作者：
Zhenghong Jiang;Steve Dai;G. E. Suh;Zhiru Zhang
专用硬件加速器正越来越多地集成到当今的计算机系统中，以实现更高的性能和能效。然而，由此产生的多样性和复杂性使确保这些加速器的安全具有挑战性。为了在保证安全性的同时降低复杂性，我们提出了一种高级综合(HLS)基础设施，该基础设施结合了静态信息流分析，以在HLS生成的硬件加速器上实施安全策略。我们的安全受限的HLS基础设施能够有效地识别显式和隐式信息泄漏。通过在行为级别检测安全漏洞，我们的工具允许设计人员在设计流程的早期阶段解决这些漏洞。我们进一步提出了一种新的合肥光源综合技术，以消除所产生的加速器中的定时通道。我们的方法能够以可验证的方式删除定时通道，同时为加速器上的高安全性任务带来较低的性能开销。
Specialized hardware accelerators are being increasingly integrated into today's computer systems to achieve improved performance and energy efficiency. However, the resulting variety and complexity make it challenging to ensure the security of these accelerators. To mitigate complexity while guaranteeing security, we propose a high-level synthesis (HLS) infrastructure that incorporates static information flow analysis to enforce security policies on HLS-generated hardware accelerators. Our security-constrained HLS infrastructure is able to effectively identify both explicit and implicit information leakage. By detecting the security vulnerabilities at the behavioral level, our tool allows designers to address these vulnerabilities at an early stage of the design flow. We further propose a novel synthesis technique in HLS to eliminate timing channels in the generated accelerator. Our approach is able to remove timing channels in a verifiable manner while incurring lower performance overhead for high-security tasks on the accelerator.