A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback
A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback
复制标题
连续时间 /spl Sigma//spl Delta/ 调制器，通过 SCR 反馈降低对时钟抖动的敏感度
DOI：
10.1109/tcsi.2005.846227
复制
发表时间：
2005
期刊：
影响因子：
--
通讯作者：
Y. Manoli
中科院分区：
文献类型：
--
作者：
M. Ortmanns;F. Gerfers;Y. Manoli
针对连续时间Σ-Δ（/spl Sigma//spl Delta/）调制器对时钟抖动敏感的问题，提出了一种改进的带电阻的开关电容结构，用于连续时间反馈数模转换器（DAC）中。抖动的灵敏度降低的模拟和证明从两个实施的三阶调制器的测量结果。此外，非理想的行为进行了分析和模拟。
This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.