Application of FPGAs to Triggering in High Energy Physics
Application of FPGAs to Triggering in High Energy Physics
复制标题
FPGA在高能物理触发中的应用
DOI：
10.25560/66689
复制
发表时间：
2018
影响因子：
5.2
通讯作者：
S. Summers
中科院分区：
文献类型：
--
作者：
S. Summers
大型强子对撞机的高亮度升级将把瞬时亮度提高到5 × 10 34 cm −2 s −1，从而使每个事件中同时发生的质子-质子碰撞（堆积）数量增加到140-200。CMS 1级触发系统将升级，并将40 MHz事件率降至750 kHz。该系统将在FPGA器件上执行快速事件重建，并在12.5 μs的延迟内选择要读出的事件。本文研究了FPGA高级编程工具Maxloger在一级触发器中的应用。一个现有的触发算法，最初开发的硬件描述语言，重新实现使用Maximizer和原来的相比。观察到输出之间的按位一致性，代码行数减少一半，代价是一些额外的FPGA资源。提出了一个建议的1级跟踪重建的硬件演示，与卡尔曼滤波器的跟踪拟合与Maximizer开发。跟踪的性能进行了研究，以及开发先进的算法，低延迟使用该工具的潜力。在高堆积事件下，该算法具有3.7 μs的延迟，实现了高跟踪效率和精确的参数分辨率。一个提升的决策树分类器，实现了几个时钟周期的推理延迟，作为一种手段来拒绝假的轨道。在1级触发器之后，在高级触发器（HLT）中在商品PC上进一步处理事件。高亮度LHC也将挑战HLT，预计需要20倍于LHC运行II期间使用的处理能力。HLT跟踪的一部分被移植到Maxeler数据流引擎（DFE），一种硬件加速技术。实现了更快的处理速率，但主机-DFE通信的初始延迟限制了性能。确定了可能加速的步骤。
The High Luminosity upgrade of the LHC will increase the instantaneous luminosity to 5 × 10 34 cm −2 s −1 , resulting in an increase in the number of simultaneous proton-proton collisions per event (pileup) to the range 140-200. The CMS Level 1 Trigger system will be upgraded, and will reduce the 40 MHz event rate to 750 kHz. The system will perform a fast event reconstruction on FPGA devices, and select events for read out within a latency of 12.5 μs. The high level FPGA programming tool MaxCompiler is investigated for use in Level 1 Trigger applications. An existing trigger algorithm, originally developed with a Hardware Description Language, is reimplemented using MaxCompiler and compared to the original. Bitwise agreement between the outputs is observed, with half as many lines of code, at the expense of some extra FPGA resources. A hardware demonstration of a proposed Level 1 track reconstruction is presented, with a Kalman Filter track fit developed with MaxCompiler. The performance of the tracking is investigated, as well as the potential for developing advanced algorithms with low latency using the tool. A high tracking efficiency, and precise parameter resolutions, are achieved with a 3.7 μs latency in high pileup events. A boosted decision tree classifier, implemented with inference latency of a few clockcycles, is presented as a means to reject fake tracks. After the Level 1 Trigger, events are further processed on commodity PCs in the High Level Trigger (HLT). The High Luminosity LHC will also challenge the HLT, which is projected to require twenty times the processing power used during LHC Run II. Part of the HLT tracking is ported to Maxeler Dataflow Engines (DFEs), a hardware acceleration technology. A faster rate of processing is achieved, but with an initial latency of the host-DFE communication that limits the performance. Steps which might yield acceleration are identified.