FPGA-Based Design Δ-Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit
FPGA-Based Design Δ-Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit
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DOI：
10.1142/s0218126615500371
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发表时间：
2015-02
期刊：
影响因子：
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通讯作者：
N. B. Ameur;N. Masmoudi;M. Loulou
中科院分区：
文献类型：
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作者：
N. B. Ameur;N. Masmoudi;M. Loulou
本文重点研究了一种适用于专业数字音频的Δ-Σ数模转换算法的综合设计。采用VHDL语言，采用自顶向下的设计方法，实现了一种快速寄存器传输级(RTL)设计。所有的RTL设计仿真、VHDL语言实现和现场可编程门阵列验证都是通过该方法快速而系统地完成的。在保持音频DAC原有精度的同时，考虑了分布式流水线、流媒体和资源共享的设计，以优化面积和速度。该设计具有精度高、处理速度快、成本低等特点。相关工作是在MatLab和QUARTUS II仿真器上完成的。
This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators.