Characterization of Long Wire Data Leakage in Deep Submicron FPGAs
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs
复制标题
深亚微米 FPGA 中长线数据泄漏的表征
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Daniel E. Holcomb
中科院分区：
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作者：
George Provelengios;Chethan Ramesh;S. B. Patil;Ken Eguro;R. Tessier;Daniel E. Holcomb
最近的研究表明，多个租户同时使用 FPGA 可能会在受害者不知情的情况下泄露敏感信息。例如，基于 SRAM 的 FPGA 中的相邻长线已被证明允许秘密数据泄露。在这项工作中，我们探索了这种信号串扰的独特特征，可用于增强或防止信息泄漏。首先，我们开发了一种机制来表征飞秒尺度上相邻导线之间存在的串扰耦合。其次，我们表明，即使 FPGA 供应商未提供此信息，也可以通过确定通道中的哪些路由资源/链路对表现出相互耦合来对通道布局进行逆向工程。为了充分表征这些影响，我们检查了在 65 至 20 nm 不同技术节点中实现的三种设备上不同类型电线上的长线耦合。我们通过实验证明，所有三个 FPGA 系列都存在明显的信息泄漏问题。
The simultaneous use of FPGAs by multiple tenants has recently been shown to potentially expose sensitive information without the victim's knowledge. For example, neighboring long wires in SRAM-based FPGAs have been shown to allow for clandestine data exfiltration. In this work, we explore distinct characteristics of this signal crosstalk that could be used to enhance or prevent information leakage. First, we develop a mechanism to characterize the crosstalk coupling that exists between neighboring wires at the femtosecond scale. Second, we show that it is possible to reverse engineer channel layouts by determining which pairs of routing resources/links in the channel exhibit coupling to each other even if this information is not provided by the FPGA vendor. To fully characterize these effects, we examine long wire coupling on different types of wires across three devices implemented in different technology nodes from 65 to 20 nm. We experimentally demonstrate that information leakage is apparent for all three FPGA families.