Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices
Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices
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DOI：
10.1109/16.760414
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发表时间：
1999-05
影响因子：
3.1
通讯作者：
S. Zhang;J. Sin;Tommy M. L. Lai;P. Ko
中科院分区：
文献类型：
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作者：
S. Zhang;J. Sin;Tommy M. L. Lai;P. Ko
提出了在高压薄膜SOI器件漂移区获得线性掺杂谱线的数值模型，并进行了实验验证。利用该模型设计并演示了具有0.15-/spl mu/m SOI层、2-/spl mu/m埋地氧化物和50-/spl mu/m漂移区的LDMOS晶体管击穿电压超过612 V。比较了击穿电压与漂移区长度的理论关系和实验关系。仿真结果与实验结果吻合较好。实验还研究了线性掺杂漂移区击穿电压与掺杂密度和掺杂浓度斜率的关系。结果表明，在具有线性掺杂漂移区的薄膜SOI器件中，为了优化击穿电压，需要一个最佳浓度斜率。最后，还描述了一种600 v CMOS兼容的SOI薄膜LDMOS工艺。
A numerical model for obtaining linear doping profiles in the drift region of high-voltage thin-film SOI devices is proposed and experimentally verified. Breakdown voltage in excess of 612 V on LDMOS transistors with 0.15-/spl mu/m SOI layer, 2-/spl mu/m buried oxide, and 50-/spl mu/m drift region is designed and demonstrated using this model. Theoretical and experimental dependence of the breakdown voltage on the drift region length are compared. Good agreement between the simulation and experimental results are obtained. Dependence of the breakdown voltage on the doping density and doping concentration slope in the linearly doped drift region is also investigated experimentally. Results indicate that an optimum concentration slope is needed in order to optimize the breakdown voltage in the thin-film SOI devices with a linear doping drift region. Finally, a 600-V CMOS compatible thin-film SOI LDMOS process is also described.