Test program synthesis for path delay faults in microprocessor cores
Test program synthesis for path delay faults in microprocessor cores
复制标题
微处理器内核路径延迟故障的测试程序综合
DOI：
10.1109/test.2000.894321
复制
发表时间：
2000
期刊：
影响因子：
--
通讯作者：
K. Cheng
中科院分区：
文献类型：
--
作者：
Wei;Angela Krstic;K. Cheng
本文解决了使用其指令集测试微处理器核心中测试路径延迟故障的问题。我们建议通过运行自动合成的测试程序来自我测试，该程序可以实现高路径延迟故障覆盖范围。本文讨论了用于合成此类测试程序的方法和原型软件框架。基于处理器的指令集体系结构，微体系结构，RTL Netlist以及栅极级的网表，对路径延迟故障进行建模，该方法通过巧妙地结合结构和指令 - 水平测试生成技术。两个微处理器的实验结果表明，可以成功生成高百分比可测试路径延迟故障的测试指令序列。
This paper addresses the problem of testing path delay faults in a microprocessor core using its instruction set. We propose to self-test a processor core by running an automatically synthesized test program which can achieve a high path delay fault coverage. This paper discusses the method and the prototype software framework for synthesizing such a test program. Based on the processor's instruction set architecture, micro-architecture, RTL netlist as well as gate-level netlist on which the path delay faults are modeled, the method generates deterministic tests (in the form of instruction sequences) by cleverly combining structural and instruction-level test generation techniques. The experimental results for two microprocessors indicate that the test instruction sequences can be successfully generated for a high percentage of testable path delay faults.