Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches
复制标题
结合网卡内和内核内方法的多级 NoSQL 缓存
DOI：
10.1109/mm.2017.3711653
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发表时间：
2017
期刊：
影响因子：
3.6
通讯作者：
Hiroki Matsutani
中科院分区：
文献类型：
--
作者：
Yuta Tokusashi;Hiroki Matsutani
基于现场可编程门阵列（fpga）的键值存储加速器已被提出，以实现比基于软件的处理更高的每瓦性能。然而，由于它们的缓存容量受到FPGA板上实现的dram的严格限制，它们的应用领域也受到限制。为了解决这个问题，作者提出了一种多层NoSQL缓存架构，该架构利用基于fpga的硬件缓存和内核内软件缓存以互补的方式进行缓存。这促使他们探索各种设计选项。仿真结果表明，与非分层设计相比，该设计降低了缓存丢失率，提高了吞吐量。
Key-value store accelerators based on field-programmable gate arrays (FPGAs) have been proposed to achieve higher performance per watt than software-based processing. However, because their cache capacity is strictly limited by DRAMs implemented on FPGA boards, their application domains are also limited. To address this issue, the authors propose a multilevel NoSQL cache architecture that utilizes both FPGA-based hardware cache and in-kernel software cache in a complementary style. This motivates them to explore various design options. Simulation results show that their design reduces the cache miss ratio and improves the throughput compared to the nonhierarchical design.