Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
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基于有源漏电流降低技术的亚阈值电源自举 CMOS 逆变器的设计
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
C. Su
中科院分区：
文献类型：
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作者：
Yingchieh Ho;Chiachi Chang;C. Su
本文简要介绍了一种工作在亚阈值电源下的自举CMOS逆变器。除了提高驱动能力外，栅极电压从-VDD到2VDD的较大摆幅抑制了亚阈值泄漏电流。与其他报道的工作相比，所提出的自举逆变器使用了更少的工作在亚阈值区域的晶体管。因此，我们的设计具有更短的延迟时间。蒙特卡罗分析结果表明，在200 mV工作电压下，在工艺和温度变化下，延迟时间的σ仅为6.3 ns。此外，采用90 nm SPRVT Low-K CMOS工艺制作了测试芯片。芯片测试结果表明，在200 mV VDD下，每级负载为200-FF的十级自举逆变器是可行的。该测试芯片在200 mV VDD下能够达到10 MHz的时钟频率，功耗为1.01μW，漏电功率为107nW。
This brief presents a bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to improving the driving ability, a large gate voltage swing from -VDD to 2VDD suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV VDD. The test chip is able to achieve 10-MHz clock rate at 200 mV VDD, the power consumption is 1.01 μW, and the leakage power is 107 nW.