Pulsed transfer etching of PS-PDMS block copolymers self-assembled in 193 nm lithography stacks.

Pulsed transfer etching of PS-PDMS block copolymers self-assembled in 193 nm lithography stacks.
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DOI:
10.1021/am504475q
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发表时间:
2014-09
影响因子:
9.5
通讯作者:
C. Girardot;S. Böhme;S. Archambault;M. Salaün;E. Latu-Romain;G. Cunge;O. Joubert;M. Zelsmann
C. Girardot;S. Böhme;S. Archambault;M. Salaün;E. Latu-Romain;G. Cunge;O. Joubert;M. Zelsmann
中科院分区:
材料科学2区
文献类型:
--
作者:
C. Girardot;S. Böhme;S. Archambault;M. Salaün;E. Latu-Romain;G. Cunge;O. Joubert;M. Zelsmann

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本文介绍了在标准的工业光刻堆叠中高-x嵌段共聚物(BCP)的图形外延及其到硅衬底中的转移。该过程包括常规的193 nm光刻、聚苯乙烯-嵌段-聚二甲基硅氧烷(PS-b-PDMS)的定向自组装和脉冲等离子体蚀刻以将所获得的特征转移到衬底中。PS-b-PDMS具有高Flory-Huggins相互作用参数(高-X),并且能够实现亚10 nm的特征尺寸。该光刻堆叠在300 mm直径的硅晶片上制造,并且由三层组成:旋涂碳(SoC)、含硅抗反射涂层(SiARC)和193 nm光刻抗蚀剂。首先使用抗蚀剂掩模通过等离子体蚀刻在SiARC/SoC堆叠中图案化60纳米深的沟槽。然后将PS-b-PDMS铺展在基底表面上。通过溶剂蒸气退火工艺诱导嵌段共聚物的定向自组装,得到了平行于衬底表面的PDMS圆柱体。基于SoC的表面化学允许有效地蚀刻到下面的硅衬底中。蚀刻工艺在专用脉冲等离子体蚀刻条件下进行。十五纳米的半间距密集线/空间的功能,获得了高达90纳米的高度。
This work presents the graphoepitaxy of high-χ block copolymers (BCP) in standard industry-like lithography stacks and their transfer into the silicon substrate The process includes conventional 193 nm photolithography, directed self-assembly of polystyrene-block-polydimethylsiloxane (PS-b-PDMS) and pulsed plasma etching to transfer the obtained features into the substrate. PS-b-PDMS has a high Flory-Huggins interaction parameter (high-χ) and is capable of achieving sub-10 nm feature sizes. The photolithography stack is fabricated on 300 mm diameter silicon wafers and is composed of three layers: spin-on-carbon (SoC), silicon-containing anti-reflective coating (SiARC) and 193 nm photolithography resist. Sixty-nanometer-deep trenches are first patterned by plasma etching in the SiARC/SoC stack using the resist mask. The PS-b-PDMS is then spread on the substrate surface. Directed self-assembly (DSA) of the BCP is induced by a solvent vapor annealing process and PDMS cylinders parallel to the substrate surface are obtained. The surface chemistry based on SoC permits an efficient etching process into the underlying silicon substrate. The etching process is performed under dedicated pulsed plasma etching conditions. Fifteen nanometer half-pitch dense line/space features are obtained with a height up to 90 nm.