A 10-50-GHz CMOS distributed step attenuator with low loss and low phase imbalance
A 10-50-GHz CMOS distributed step attenuator with low loss and low phase imbalance
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DOI：
10.1109/jssc.2007.907205
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发表时间：
2007-11-01
影响因子：
5.4
通讯作者：
Rebeiz, Gabriel M.
中科院分区：
文献类型：
--
作者：
Min, Byung-Wook;Rebeiz, Gabriel M.
本文介绍了一种低相位不平衡的10-50 ghz低损耗分布式CMOS阶跃衰减器的设计与测量。衰减由12个nMOS压敏电阻控制，nMOS寄生在合成传输线中被吸收，从而获得较宽的带宽。探讨了压敏电阻之间的电距离，以使分布式衰减器的尺寸最小，并提出了一种平衡插入相位的方法。33 ~ 37 GHz时，衰减状态损耗最小为2.1 dB，衰减状态损耗最大为13.0 dB。衰减器的最大衰减范围为11 dB，步进为0.9 dB（13种状态）。在dc - 50ghz的所有衰减状态下，均方根相位不平衡小于3度。衰减器不消耗任何静态功率，在20ghz时输入1db压缩点为5dbm（定义为最大衰减范围下降1db）。不包括焊盘的总芯片尺寸为200 x 750 μ m(2) （0.15 mm(2)）。
This paper presents the design and measurement of a 10-50-GHz low-loss distributed CMOS step attenuator with low phase imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion phase is presented. At 33-37 GHz, the minimum attenuation state loss is 2.1 dB, and the maximum attenuation state loss is 13.0 dB. The attenuator has a maximum attenuation range of 11 dB with 0.9-dB steps (13 states). The rms phase imbalance is less, than 3 degrees at DC-50 GHz for all attenuation states. The attenuator does not consume any static power and the input 1-dB compression point is 5 dBm (defined as the 1-dB drop in the maximum attenuation range) at 20 GHz. The total chip size excluding pads is 200 x 750 mu m(2) (0.15 mm(2)).