A structured approach to post-silicon validation and debug using symbolic quick error detection
A structured approach to post-silicon validation and debug using symbolic quick error detection
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使用符号快速错误检测进行硅后验证和调试的结构化方法
DOI：
10.1109/test.2015.7342397
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
S. Mitra
中科院分区：
文献类型：
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作者：
David C. Lin;Eshan Singh;Clark W. Barrett;S. Mitra
在硅后验证和调试期间，制造的集成电路（ic）在实际系统环境中进行测试，以检测和修复设计缺陷（bug）。现有的后硅验证和调试技术大多是特别的，通常涉及手动步骤。这种特殊的方法不能随着集成电路复杂性的增加而扩展。我们提出了符号快速错误检测（符号QED），一种结构化的后硅验证和调试方法。符号QED以协调的方式组合了以下步骤：快速错误检测（QED）测试，快速检测错误，具有较短的错误检测延迟和高覆盖率。2. 形式化分析技术，用于定位bug，并在检测到相应的bug后生成最小长度的bug跟踪。我们使用OpenSPARC T2（一个5亿晶体管的开源多核片上系统（SoC）设计），并使用各种最先进的商业多核SoC中出现的“困难”逻辑错误场景，展示了符号QED的实用性和有效性。我们的结果表明，符号QED:(i)是全自动的（不像今天使用的手工技术，可能非常耗时和昂贵）；（ii）与可能需要数天（甚至数月）的手工方法或通常需要数天或完全失败的大型设计的正式技术相比，只需几个小时；（iii）生成反例（用于激活和检测逻辑错误），比传统技术产生的反例缩短最多6个数量级；并且，（iv）不需要任何额外的硬件。
During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Existing post-silicon validation and debug techniques are mostly ad hoc and often involve manual steps. Such ad hoc approaches cannot scale with increasing IC complexity. We present Symbolic Quick Error Detection (Symbolic QED), a structured approach to post-silicon validation and debug. Symbolic QED combines the following steps in a coordinated fashion: 1. Quick Error Detection (QED) tests that quickly detect bugs with short error detection latencies and high coverage. 2. Formal analysis techniques to localize bugs and generate minimal-length bug traces upon detection of the corresponding bugs. We demonstrate the practicality and effectiveness of Symbolic QED using the OpenSPARC T2, a 500-million-transistor open-source multicore System-on-Chip (SoC) design, and using "difficult" logic bug scenarios that occurred in various state-of-the-art commercial multicore SoCs. Our results show that Symbolic QED: (i) is fully automatic (unlike manual techniques in use today that can be extremely time-consuming and expensive); (ii) requires only a few hours in contrast to manual approaches that might take days (or even months) or formal techniques that often take days or fail completely for large designs; (iii) generates counter-examples (for activating and detecting logic bugs) that are up to 6 orders of magnitude shorter than those produced by traditional techniques; and, (iv) does not require any additional hardware.