Modeling of Integrated Circuit Yield Using a Spatial Nonhomogeneous Poisson Process
Modeling of Integrated Circuit Yield Using a Spatial Nonhomogeneous Poisson Process
复制标题
使用空间非齐次泊松过程对集成电路成品率进行建模
DOI：
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发表时间：
2011
影响因子：
2.7
通讯作者：
Chunghun Ha
中科院分区：
文献类型：
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作者：
Jung Yoon Hwang;W. Kuo;Chunghun Ha
提出了一种新的基于空间点工艺的集成电路成品率模型。晶片上缺陷密度随位置的变化可用空间非均匀泊松过程来模拟。成品率模型的强度函数描述了晶片上的缺陷图案。因此，该模型不同于现有的复合泊松屈服模型，其描述缺陷空间分布的能力有所不同。使用基于模型的聚类，可以将包含制造过程变化信息的可分配原因的缺陷聚类与其他缺陷聚类区分开来。该模型考虑了晶片间缺陷密度的变化以及缺陷尺寸对缺陷导致电路故障概率的影响。用模拟数据和实际数据验证了新的产量模型的性能。仿真结果表明，新的产量模型比复合泊松产量模型具有更好的预测效果。
This paper proposes a new yield model for integrated circuits using a spatial point process. The defect density variation by location on a wafer is modeled by a spatial nonhomogeneous Poisson process. The intensity function of the yield model describes the defect pattern on wafers. As a result, the model differs from the existing compound Poisson yield models in its capability to describe the spatial defect distribution. Using model-based clustering, the defect clusters from assignable causes, which contain the information about the variations of manufacturing processes, can be classified from others. The proposed model considers the defect density variation among wafers and the impact of defect size on the probability of a defect causing the circuit failure. The performance of the new yield model is verified using simulated data and real data. Simulation results show that the new yield model performs better than a compound Poisson yield model.