A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter
A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter
复制标题
12 位 1Msample/s 电容器误差平均流水线 A/D 转换器
DOI：
10.1109/4.90028
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发表时间：
1988
影响因子：
5.4
通讯作者：
K. Lakshmikumar
中科院分区：
文献类型：
--
作者：
B. Song;M. Tompsett;K. Lakshmikumar
应用电容器误差平均技术来执行高分辨率流水线模数 (A/D) 转换器所需的精确乘二 (*2) 功能。由电容器失配和开关馈通引起的误差在模拟域中得到校正，而无需使用数字校准和/或微调。已经制作并评估了一种差分流水线 A/D 转换器，该转换器可实现 1 Msample/s 的吞吐率和 12 位线性度。使用双多晶 1.75μm CMOS 工艺实现的原型流水线 A/D 转换器在 5V 单电源下功耗为 400mW，占用 14mm/sup 2/，包括所有数字逻辑和输出缓冲器。 >
A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75- mu m CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm/sup 2/, including all digital logic and output buffers. >