A low-complexity LDPC decoder for NAND flash applications
A low-complexity LDPC decoder for NAND flash applications
复制标题
DOI：
10.1109/iscas.2014.6865103
复制
发表时间：
2014-06
期刊：
影响因子：
--
通讯作者：
Mao-Ruei Li;Hsueh-Chih Chou;Yeong-Luh Ueng;Yun Chen
中科院分区：
文献类型：
--
作者：
Mao-Ruei Li;Hsueh-Chih Chou;Yeong-Luh Ueng;Yun Chen
本文提出了一种高效的基于最小和的高速率低密度奇偶校验码解码器，其中第一最小值和第二最小值存储在寄存器中。为了满足NAND闪存应用对成本的严格要求，我们为第一和第二最小值提供了不同的上限。此外，我们对第二个最小值采用非均匀量化，以降低存储复杂度。为了提高错误率性能，根据前两个最小值之差确定归一化因子。使用所提出的技术，可以在不降低错误率性能的情况下实现门数减少13.36%。对一个速率为0.896长度为18624的分层解码器的实现结果表明，该解码器在时钟频率为166 MHz、门数为620K的情况下可以实现765.24 Mb/s的吞吐量。
This paper presents an efficient min-sum-based decoder for high-rate low-density parity-check (LDPC) codes, where the first minimum and second minimum values are stored in registers. In order to meet a strict cost requirement imposed by NAND flash applications, we provide different upper limits for the first and second minimum values. Furthermore, we use non-uniform quantization for the second minimum value so as to reduce storage complexity. In order to enhance the error-rate performance, the normalization factor is determined based on the difference between the first two minimum values. Using the proposed techniques, a reduction in gate count of 13.36% can be achieved without suffering any degradation in error-rate performance. The implementation results for a rate-0.896 length-18624 layered decoder show that this decoder can achieve a throughput of 765.24 Mb/s at a clock frequency of 166 MHz with a gate count of 620K.