Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques
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DOI:
10.1109/tns.2016.2525735
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发表时间:
2016-07
影响因子:
1.8
通讯作者:
E. Chielle;F. Rosa;G. Rodrigues;L. Tambara;Jorge Tonfat;E. Macchione;F. Aguirre;N. Added;N. Medina;V. Aguiar;M. Silveira;Luciano Ost;R. Reis;S. Cuenca-Asensi;F. Kastensmidt
E. Chielle;F. Rosa;G. Rodrigues;L. Tambara;Jorge Tonfat;E. Macchione;F. Aguirre;N. Added;N. Medina;V. Aguiar;M. Silveira;Luciano Ost;R. Reis;S. Cuenca-Asensi;F. Kastensmidt
中科院分区:
工程技术3区
文献类型:
--
作者:
E. Chielle;F. Rosa;G. Rodrigues;L. Tambara;Jorge Tonfat;E. Macchione;F. Aguirre;N. Added;N. Medina;V. Aguiar;M. Silveira;Luciano Ost;R. Reis;S. Cuenca-Asensi;F. Kastensmidt

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ARM处理器是嵌入式系统的领导者,提供高性能计算、能效和低成本。由于这个原因,人们对其在航空航天工业中的应用很感兴趣。然而,亚微米技术的使用增加了对辐射诱发瞬态故障的敏感性。因此,减轻软错误已成为一个主要问题。软件实现硬件容错(SIHFT)技术是一种保护处理器免受软错误侵害的低成本方法。另一方面,它们在执行时间和内存方面造成了很高的开销,从而增加了能耗。在这项工作中,我们实现了一套基于不同冗余和检查规则的软件技术。此外,还包括一种保护程序执行流的低开销技术。测试使用ARM Cortex-A9处理器执行。进行了模拟断层注入活动和重离子辐射试验。结果评估了故障检测、执行时间和内存占用之间的权衡。与以前报道的技术相比,它们显示了开销的显著改进。
ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.