Spiking Neural Networks in Spintronic Computational RAM
Spiking Neural Networks in Spintronic Computational RAM
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DOI：
10.1145/3475963
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发表时间：
2020-06
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通讯作者：
Husrev Cilasun;Salonik Resch;Z. Chowdhury;Erin Olson;Masoud Zabihi;Zhengyang Zhao;Thomas J. Peterson;K. Parhi;Jianping Wang;S. Sapatnekar;Ulya R. Karpuzcu
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作者：
Husrev Cilasun;Salonik Resch;Z. Chowdhury;Erin Olson;Masoud Zabihi;Zhengyang Zhao;Thomas J. Peterson;K. Parhi;Jianping Wang;S. Sapatnekar;Ulya R. Karpuzcu
尖峰神经网络（SNN）代表了一种生物启发的计算模型，能够模拟人脑和类脑结构中的神经计算。主要承诺是非常低的能耗。然而，基于经典冯诺依曼架构的SNN硬件加速器通常无法大规模有效地解决苛刻的计算和数据传输要求。在这篇文章中，我们提出了一种有前途的替代方案，以克服可扩展性的限制，基于内存中SNN加速器的网络，与代表性的ASIC解决方案相比，它可以减少高达150.25=的能耗。能源的显着减少来自硬件设计的两个关键方面，以最大限度地减少数据通信开销：（1）每个节点代表一个基于自旋电子计算RAM阵列的内存中SNN加速器，以及（2）一种新型的De Bruijn图形基于架构建立SNN阵列连接。
Spiking Neural Networks (SNNs) represent a biologically inspired computation model capable of emulating neural computation in human brain and brain-like structures. The main promise is very low energy consumption. Classic Von Neumann architecture based SNN accelerators in hardware, however, often fall short of addressing demanding computation and data transfer requirements efficiently at scale. In this article, we propose a promising alternative to overcome scalability limitations, based on a network of in-memory SNN accelerators, which can reduce the energy consumption by up to 150.25= when compared to a representative ASIC solution. The significant reduction in energy comes from two key aspects of the hardware design to minimize data communication overheads: (1) each node represents an in-memory SNN accelerator based on a spintronic Computational RAM array, and (2) a novel, De Bruijn graph based architecture establishes the SNN array connectivity.