Integrating RTS noise into circuit analysis
Integrating RTS noise into circuit analysis
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DOI：
10.1109/iscas.2009.5117816
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发表时间：
2009-05
期刊：
影响因子：
--
通讯作者：
T. Tang;A. Murray
中科院分区：
文献类型：
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作者：
T. Tang;A. Murray
提出了一种将随机电报信号 (RTS) 噪声纳入电路分析的新方法。该方法的目的是让集成电路设计人员能够研究其电路对 RTS 噪声的敏感性，从而最大限度地减少其影响。在这项工作中，使用了从基于随机掺杂的三维“原子”模拟中提取的紧凑模型。这些模型定义了 35nm CMOS 技术器件，在 Si-SiO2 界面处具有单电荷捕获，从而定义了 RTS 噪声的幅度。 RTS 噪声的时序参数是根据 Shockley-Reed-Hall 统计数据预测的。该方法在稳态和时变偏置条件下应用于测试电路，以四象限 Chible 乘法器为例。还报告了器件变异性（基于蒙特卡罗方法）和温度扫描的仿真结果。
A new methodology to include Random Telegraph Signals (RTS) noise in circuit analysis is proposed. The aim of this methodology is to allow integrated circuit designers to study the sensitivity of their circuits to RTS noise and thus minimise the impact of it. In this work, compact models extracted from three-dimensional ‘atomistic’ simulations based on random doping were used. These models define 35nm CMOS technology devices with single charge trapping at the Si-SiO2 interface, and therefore the amplitude of RTS noise. The timing parameters of RTS noise were predicted based on the Shockley-Reed-Hall statistics. The methodology was applied to a test circuit, four-quadrant Chible multiplier as an example, under both steady-state and time-varying bias conditions. Simulation results on variability in devices (based on Monte Carlo methods) and temperature sweep are also reported.