Efficient CMOL Gate Designs for Cryptography Applications
Efficient CMOL Gate Designs for Cryptography Applications
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DOI：
10.1109/tnano.2008.2011812
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发表时间：
2009-05
影响因子：
2.4
通讯作者：
Z. Abid;A. Alma'aitah;M. Barua;W. Wang
中科院分区：
文献类型：
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作者：
Z. Abid;A. Alma'aitah;M. Barua;W. Wang
为有效实现密码算法，提出了一种新型互补金属氧化物半导体纳米(CMOL)混合电路。本研究的创新之处在于利用两种类型的纳米结器件和CMOS微结构来构建密码集成电路。特别是，高效的电阻结异或门和二极管结异或/与门被开发成高级加密标准(AES)密码IC的相应模块的构建模块。与现有的AES系统的CMOL实现相比，它们在功耗、面积和时间延迟方面分别减少了79%、43%和53%。与AES的现场可编程纳米线互连(FPNI)设计相比，功耗提高了56%，面积和时延分别减少了92%和15%。本文提出的电路研究也充分利用了最新的制造成果，为未来密码集成电路的发展提供了一种可行的CMOS-Nano混合解决方案。
This paper introduces new hybrid complementary metal-oxide-semiconductor (CMOS)-nano (CMOL) circuits for efficient implementation of cryptographic algorithms. The novelty of this study is to utilize two types of nanojunction devices with CMOS to build the crypto IC. In particular, efficient XOR gate with resistive junctions and XOR/AND gates with diode-like junctions are develop to be used as building blocks of the corresponding modules of the Advanced Encryption Standard (AES) crypto IC. They allow a reduction of 79%, 43%, and 53% in power dissipation, area, and time delay compared to the existing CMOL implementation of AES system. When compared to field-programmable nanowire interconnect (FPNI) design of AES, a 56% increase in power dissipation was recorded in order to achieve a 92% and 15% reduction in area and time delay. This proposed circuit study also leverages the recent fabrication results, which is a feasible CMOS-nano hybrid solution for future crypto IC development.