Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata
复制标题
使用参数定时自动机验证存储电路的通用架构
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
Weiwen Xu
中科院分区：
文献类型：
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作者：
R. Chevallier;Emmanuelle Encrenaz;L. Fribourg;Weiwen Xu
Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This allows us to check two different implementations of this architecture.
