Extremely Low ON-Resistance SiC Cascode Configuration Using Buried-Gate Static Induction Transistor
Extremely Low ON-Resistance SiC Cascode Configuration Using Buried-Gate Static Induction Transistor
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DOI：
10.1109/led.2018.2878933
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发表时间：
2018-10
影响因子：
4.9
通讯作者：
K. Yano;Yasunori Tanaka;M. Yamamoto
中科院分区：
文献类型：
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作者：
K. Yano;Yasunori Tanaka;M. Yamamoto
利用碳化硅（SiC）埋栅静电感应晶体管（BGSIT）和低压Si-MOSFET（SiC-BGSIT共源共栅），首次实现了漏源击穿电压为978 V的35 A共源共栅结构。SiC-SIT与Si-MOSFET一起安装在最初设计的树脂4pin封装中。室温下器件的导通电阻R_{DS（ON）}$为34.3 m Ω $，是同类器件的50%.揭示了R_{DS（ON）}$和门阈值电压的温度依赖性。有人认为，与具有类似额定值的SiC-JFET共源共栅相比，BGSIT共源共栅具有软$\textit {dV}_{\text {ds}}/\textit {dt}$特性，开关损耗相对较小。
A 35-A cascode configuration of a drain-to-source breakdown voltage of 978 V utilizing an silicon carbide (SiC) buried gate static induction transistor (BGSIT) and low voltage Si-MOSFET (SiC-BGSIT cascode) has been experimentally demonstrated for the first time. The SiC-SIT is mounted with the Si-MOSFET in an originally designed resin 4pin package. The ON-resistance $R_{\text {DS(ON)}}$ of this device exhibits 34.3 $\text{m}\Omega $ at room temperature, which is 50% of the commercial SiC MOSFET of the similar rating. The temperature dependence of $R_{\text {DS(ON)}}$ and gate threshold voltage has been revealed. It has been suggested that when compared with the SiC-JFET cascode with the similar rating, the BGSIT cascode has a soft $\textit {dV}_{\text {ds}}/\textit {dt}$ property with a relatively small switching loss.