Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
复制标题
用于硬件仿真的基于自动机的高效断言检查器综合 SERE
DOI：
10.1109/aspdac.2007.358006
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发表时间：
2007
期刊：
影响因子：
--
通讯作者：
Z. Zilic
中科院分区：
文献类型：
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作者：
M. Boule;Z. Zilic
在本文中，我们提出了一种从顺序扩展正则表达式（SERE）生成检查器电路的方法。此类序列构成了日益常用的基于断言的验证（ABV）语言的核心。一个能够将断言转换为高效电路的检查器生成器允许在硬件仿真中采用ABV。为了实现该目标，我们引入了序列融合和长度匹配交集的算法，这是两种通常不在正则表达式上使用的SERE操作符。我们还开发了一种生成故障检测自动机的算法，这是将正则表达式扩展用于ABV的关键概念，并且提出了我们的高效符号编码。对复杂序列的实验表明，我们的工具优于已知的最佳检查器生成器。
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used assertion-based verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.