Pipelined FPGA Adders
Pipelined FPGA Adders
复制标题
流水线 FPGA 加法器
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
B. Pasca
中科院分区：
文献类型：
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作者：
F. D. Dinechin;Hong Diep Nguyen;B. Pasca
加法运算是一种通用的构造块，像四精度浮点或椭圆曲线密码这样的应用现在要求的精度远远超过64位。本研究探讨FPGA上管线式大精度加法器在尺寸、延迟与频率之间的平衡。它比较了三种流水线加法器架构：经典的流水线纹波进位加法器，减少寄存器数量的变化，以及能够以可比价格提供较低延迟加法的进位选择加法器的FPGA特定实现。对于这些架构中的每一个，资源估计模型被定义，并且在加法器生成器中使用，该加法器生成器考虑目标FPGA、目标操作频率和加法位宽来选择最佳架构。
Integer addition is a universal building block, and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. This study explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA. It compares three pipelined adder architectures: the classical pipelined ripple-carry adder, a variation that reduces register count, and an FPGA-specific implementation of the carry-select adder capable of providing lower latency additions at a comparable price. For each of these architectures, resource estimation models are defined, and used in an adder generator that selects the best architecture considering the target FPGA, the target operating frequency, and the addition bit width.