Three-dimensional system-in-package using stacked silicon platform technology
Three-dimensional system-in-package using stacked silicon platform technology
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DOI：
10.1109/tadvp.2005.852895
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发表时间：
2005-08
影响因子：
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通讯作者：
V. Kripesh;Seung Wook Yoon;V. Ganesh;Navas Khan;M. D. Rotaru;Wang Fang;M. Iyer
中科院分区：
文献类型：
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作者：
V. Kripesh;Seung Wook Yoon;V. Ganesh;Navas Khan;M. D. Rotaru;Wang Fang;M. Iyer
本文提出了一种利用硅载体制造三维系统级封装（SiP）的新方法，这种硅载体可以将已知的好骰子与集成冷却解决方案集成在一起。该堆叠模块的骨干是制造具有通孔导电互连的硅载流子。本文讨论了湿硅蚀刻法制造硅通孔互连的设计、工艺和装配。在设计公差范围内实现了硅载流子焊接通孔互连的工艺优化。设计和建模方法，以优化封装的电气方面的堆叠模块，以实现更少的互连寄生。采用单相和两相冷却解决方案的3d堆叠模块集成冷却解决方案也演示了用于大功率应用。已知优良的带菊花链的薄倒装芯片器件通过倒装工艺制造并连接到硅载体上，使其在电气测试后成为已知优良的载体。单个已知的良好运营商垂直整合形成3-D SiP。
In this paper, a novel method of fabricating three-dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.