PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms
PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms
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DOI：
10.1109/isca.2018.00015
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发表时间：
2018-06
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通讯作者：
Prakalp Srivastava;Mingu Kang;Sujan Kumar Gonugondla;Sungmin Lim;Jungwook Choi;Vikram S. Adve;N. Kim
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作者：
Prakalp Srivastava;Mingu Kang;Sujan Kumar Gonugondla;Sungmin Lim;Jungwook Choi;Vikram S. Adve;N. Kim
模拟/混合信号计算机学习（ML）加速器利用模拟/混合信号电路的独特计算能力和ML算法的固有误差耐受性比数字ML加速器获得更高的能量效率。不幸的是，这些模拟/混合信号ML加速器缺乏可编程性，甚至指令设置界面，以支持多种ML算法或能够对Energy-VS-Accuracy Cracy Fraceoffs进行基本的软件控制。我们提出了Promise，这是从指令集体系结构（ISA）到高级语言编译器的第一个可编程混合信号加速器的端到端设计，用于加速不同的ML算法。我们首先在支持这些操作的可编程混合信号加速器方面确定了广泛使用的ML算法和关键约束的普遍操作。其次，基于该分析，我们提出了一个ISA，其具有硅验证的组件构建的承诺体系结构用于混合信号操作。第三，我们开发了一个可以使用高级编程语言（Julia）描述的ML算法的编译器，并生成了Promise代码，其IR设计既是语言中性的，又是摘要不必要的硬件详细信息。第四，我们展示了编译器如何映射神经网络应用程序的应用程序级别的错误公差规范，直到低级硬件参数（每个应用程序任务的摆动电压）以最大程度地减少能耗。我们的实验表明，即使在特定ML算法的固定功能数字ASIC中，也可以在能源效率的数字ASIC上加速不同的ML算法，并且编译器优化即使只有1％的额外误差即使只有1％的额外误差也可以实现大量的额外节能。
Analog/mixed-signal machine learning (ML) accelerators exploit the unique computing capability of analog/mixed-signal circuits and inherent error tolerance of ML algorithms to obtain higher energy efficiencies than digital ML accelerators. Unfortunately, these analog/mixed-signal ML accelerators lack programmability, and even instruction set interfaces, to support diverse ML algorithms or to enable essential software control over the energy-vs-accuracy tradeoffs. We propose PROMISE, the first end-to-end design of a PROgrammable MIxed-Signal accElerator from Instruction Set Architecture (ISA) to high-level language compiler for acceleration of diverse ML algorithms. We first identify prevalent operations in widely-used ML algorithms and key constraints in supporting these operations for a programmable mixed-signal accelerator. Second, based on that analysis, we propose an ISA with a PROMISE architecture built with silicon-validated components for mixed-signal operations. Third, we develop a compiler that can take a ML algorithm described in a high-level programming language (Julia) and generate PROMISE code, with an IR design that is both language-neutral and abstracts away unnecessary hardware details. Fourth, we show how the compiler can map an application-level error tolerance specification for neural network applications down to low-level hardware parameters (swing voltages for each application Task) to minimize energy consumption. Our experiments show that PROMISE can accelerate diverse ML algorithms with energy efficiency competitive even with fixed-function digital ASICs for specific ML algorithms, and the compiler optimization achieves significant additional energy savings even for only 1% extra errors.