A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI
A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI
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采用 22nm FD-SOI 封装的体偏置比较器架构的单通道 18.5 GS/s 5 位闪存 ADC
DOI：
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发表时间：
2019
期刊：
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通讯作者：
F. Gerfers
中科院分区：
文献类型：
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作者：
Nima Lotfi;Pedro Lehmann Ibáñez;Marcel Runge;F. Gerfers
本文提出了一种采用比较器阱体偏置技术的Flash ADC架构，以消除经典的差分-差分放大器（DDA）和高功耗基准电压源阶梯，从而实现显著的功耗节省。DDA需要两个差分对，一个用于实际输入信号，另一个用于参考电压，而所提出的比较器技术仅使用单个差分对用于输入信号，从而将高功耗ADC的功耗降低约10%。百分之五十此外，所提出的快闪ADC的快闪ADC参考电平通过改变输入晶体管阈值电压来产生。采用的22 nm FD-SOI工艺提供了约为1.5V的阈值电压调谐增益。85 mV/V。使用3V电容性电荷泵，可实现500 mVppd的标称满量程范围。这样，所提出的方法还消除了比较器反冲，从而消除了低阻抗要求，以保证基准电压阶梯的建立。所采用的技术提供了从输入器件的栅极到背栅极的强隔离。所提出的技术被采用在一个5位18.5 GS/s的闪存ADC。采样保持沿着隔离前端输入缓冲器提供28 GHz输入带宽。前端缓冲器和SC电荷泵采用1.5V电源供电，而所有其他构建模块（比较器和时钟树）采用0.9V电源供电。总功耗为140 mW，包括时钟缓冲器。该ADC在低频和奈奎斯特输入频率下的SNDR和SFDR分别为31 dB和43 dBc和28.5dB和40 dBc
This paper presents a flash ADC architecture employing a comparator well-body biasing technique to eliminate the classical differential-difference amplifier (DDA) as well as the power-hungry reference ladder to enable significant power savings. DDAs require two differential pairs, one for the actual input signal and the other for the reference voltage whereas the proposed comparator technique merely uses a single differential pair for the input signal reducing the power consumption of the power-hungry preamplifier by approx. 50%. Furthermore, the flash ADC reference levels of the presented flash ADC, are generated by altering the input transistor threshold voltages. The adopted 22nm FD-SOI technology provides a threshold voltage tuning gain of approx. 85mV/V. Using a 3V capacitive charge-pump, a nominal full-scale range of 500 mVppd is achieved. This way, the proposed method also eliminates comparator kickback and therewith the low impedance requirement to guarantee settling of the reference ladder. The adopted technology provides a strong isolation from the gate to the back-gate of the input devices. The proposed techniques are adopted in a 5-bit 18.5 GS/s flash ADC. The track-and-hold along with the isolating front-end input buffer provides 28 GHz input bandwidth. The front-end buffer and SC charge pump operate from a 1.5V power supply while all other building blocks (comparator and clock tree) operate from a 0.9V power supply. The total power consumption is 140mW including clock buffers. The ADC achieves a SNDR and SFDR of 31dB and 43 dBc and 28.5dB and 40 dBc respectively at low and Nyquist input frequencies