FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method
FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method
复制标题
有限元法稀疏矩阵向量乘法的 FPGA 架构和实现
DOI：
10.1016/j.cpc.2007.11.014
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
W. Gross
中科院分区：
文献类型：
--
作者：
Yousef El;D. Fernandez;Evgueni Souleimanov;D. Giannacopoulos;W. Gross
有限元法（FEM）是一种计算密集型的科学和工程分析工具，从结构工程到电磁模拟都有广泛的应用。浮点性能的趋势正在向现场可编程门阵列（fpga）的方向发展，因此科学界对利用该技术的兴趣越来越大。我们提出了一种基于fpga的稀疏矩阵矢量乘法器（SMVM）的架构和实现，用于由FEM应用产生的大型稀疏方程组的迭代解。有限元矩阵显示特定的稀疏模式，可以用来提高硬件设计的效率。我们的架构利用FEM矩阵稀疏结构来实现性能和硬件资源需求之间的平衡，依靠外部SDRAM进行数据存储，同时利用fpga计算资源以流式通过收缩方法。该体系结构基于处理元素（pe）的流水线线性阵列，加上面向硬件的矩阵条带算法和分区方案，使其能够在不改变体系结构中pe数量的情况下处理任意大的矩阵。因此，该架构仅受FPGA可用的外部RAM数量的限制。实现的smvm流水线原型包含8个pe，时钟频率为110 MHz，峰值性能为1.76 GFLOPS。对于当前FPGA系统典型的8 GB/s内存带宽，该架构可以实现1.5 GFLOPS的持续性能。使用管道的多个实例，可以实现峰值的线性缩放和持续的性能。我们的流通架构提供了一个额外的优势，即支持迭代解决技术（如共轭梯度方法）所需的SMVM计算的迭代实现，避免了由于FPGA内部存储器中的数据加载和设置而导致的初始化时间。
The Finite Element Method (FEM) is a computationally intensive scientific and engineering analysis tool that has diverse applications ranging from structural engineering to electromagnetic simulation. The trends in floating-point performance are moving in favor of Field-Programmable Gate Arrays (FPGAs), hence increasing interest has grown in the scientific community to exploit this technology. We present an architecture and implementation of an FPGA-based sparse matrix–vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations arising from FEM applications. FEM matrices display specific sparsity patterns that can be exploited to improve the efficiency of hardware designs. Our architecture exploits FEM matrix sparsity structure to achieve a balance between performance and hardware resource requirements by relying on external SDRAM for data storage while utilizing the FPGAs computational resources in a stream-through systolic approach. The architecture is based on a pipelined linear array of processing elements (PEs) coupled with a hardware-oriented matrix striping algorithm and a partitioning scheme which enables it to process arbitrarily big matrices without changing the number of PEs in the architecture. Therefore, this architecture is only limited by the amount of external RAM available to the FPGA. The implemented SMVM-pipeline prototype contains 8 PEs and is clocked at 110 MHz obtaining a peak performance of 1.76 GFLOPS. For 8 GB/s of memory bandwidth typical of recent FPGA systems, this architecture can achieve 1.5 GFLOPS sustained performance. Using multiple instances of the pipeline, linear scaling of the peak and sustained performance can be achieved. Our stream-through architecture provides the added advantage of enabling an iterative implementation of the SMVM computation required by iterative solution techniques such as the conjugate gradient method, avoiding initialization time due to data loading and setup inside the FPGA internal memory.