Analog IC Reliability in Nanometer CMOS
Analog IC Reliability in Nanometer CMOS
复制标题
纳米 CMOS 中的模拟 IC 可靠性
DOI：
10.1007/978-1-4614-6163-0
复制
发表时间：
2013
期刊：
影响因子：
--
通讯作者：
G. Gielen
中科院分区：
文献类型：
--
作者：
E. Maricau;G. Gielen
本书着重于模拟电路老化的建模、仿真和分析。首先，所有重要的纳米CMOS物理效应导致电路的不可靠性进行了审查。然后讨论了用于电路仿真的晶体管老化紧凑模型，并解释和比较了几种有效的电路可靠性仿真方法。最后，研究了晶体管老化对模拟电路的影响。老化弹性和老化免疫电路的识别和技术缩放的影响进行了讨论。本书中描述的模型和仿真技术旨在帮助器件工程师、电路设计师和EDA社区理解和减轻老化效应对纳米CMOS IC的影响。
This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed. The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.