Single-chip multiprocessor integrating quadruple 8-Way VLIW processors with interface timing analysis considering power supply noise
Single-chip multiprocessor integrating quadruple 8-Way VLIW processors with interface timing analysis considering power supply noise
复制标题
单芯片多处理器集成了四个 8 路 VLIW 处理器，具有考虑电源噪声的接口时序分析
DOI：
10.1145/1118299.1118429
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
A. Suga
中科院分区：
文献类型：
--
作者：
Satoshi Imai;Atsuki Inoue;Motoaki Matsumura;Kenichi Kawasaki;A. Suga
本文介绍了一款集成四核的51.2 Gop、1.0 GB/S-DMA单片多处理器，并对其进行了电源完整性分析。我们的多处理器设计用于解码MP@HL流，而不需要任何专用电路。要实现如此高的性能，数据吞吐量和处理能力是重要的，需要大量的高速I/O。但是，这会产生很高的电源噪音。然后应用一个考虑电源噪声的接口时序裕度分析工具，成功地对LSI设计和印刷电路板设计进行了合理的限制。在2ch64位主存2ch266 MHz和64位系统总线178 MHz的情况下，我们成功地实现了处理器在533 MHz下的运行
This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multiprocessor integrating quadruple cores and proposes a power integrity analysis. Our multiprocessor is designed to decode MP@HL streams without any dedicated circuits. To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of high speed I/Os. However, this makes for a high level of power supply noise. We then applied an interface timing margin analysis tool that took power supply noise into account, and succeeded in putting reasonable restrictions on LSI design, as well as that for the printed circuit board. As a result, we succeeded in operating the processor at 533MHz with the 2ch 64bit main memory IF at 266MHz and 64bit system bus at 178MHz
具有衰减极点的宽带微带线BPF的实验研究-滤波器结构中分布式抽头耦合谐振器的利用-
DOI：
--
发表时间：
2006
期刊：
IEICE Technical Report vol. 105, no. 522
影响因子：
--
作者：
K. Tanii;F. Nishimura;K. Sasabe;Y. Ueno;K. Wada;T. Iwasaki
通讯作者：
T. Iwasaki