Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection
Flash ADC Utilizing Offset Voltage Variation With Order Statistics Based Comparator Selection
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DOI：
10.1109/isqed51717.2021.9424288
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发表时间：
2021-04
期刊：
影响因子：
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通讯作者：
T. Kitamura;Mahfuzul Islam;T. Hisakado;O. Wada
中科院分区：
文献类型：
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作者：
T. Kitamura;Mahfuzul Islam;T. Hisakado;O. Wada
无线通信系统需要高速Flash ADC。然而，在亚微米工艺中，失调电压的变化严重影响了面积、功率和线性度之间的平衡。本文提出了一种闪存ADC架构，利用失调电压的变化，以减少面积和功耗，消除基准电压产生。所提出的架构利用失调电压作为参考，选择适当的比较器后，片上校准。片内校准基于顺序统计量执行，可在时域中评估失调电压。我们验证了我们提出的架构HSPICE模拟的基础上，商业65纳米工艺。我们提出的架构实现了一个5位ADC的功耗小于1 mW，在2 GS/s的操作，不包括编码器。
High-speed flash ADCs are required for wireless communication systems. However, the trade-off between area, power, and linearity suffers severely by offset voltage variation in sub-micron process. This paper proposes a flash ADC architecture that utilizes the offset voltage variation to reduce area and power consumption by eliminating reference generation. The proposed architecture utilizes offset voltages as references by selecting the appropriate comparators after an on-chip calibration. The on-chip calibration is performed based on order statistics that allows evaluating offset voltages in the time-domain. We verify our proposed architecture by HSPICE simulation based on a commercial 65 nm process. Our proposed architecture realizes a 5-bit ADC with the power consumption of less than 1 mW at 2 GS/s of operation, excluding the encoder.