Digital dual mixer time difference for sub-nanosecond time synchronization in Ethernet
Digital dual mixer time difference for sub-nanosecond time synchronization in Ethernet
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DOI：
10.1109/freq.2010.5556289
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发表时间：
2010-06
期刊：
影响因子：
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通讯作者：
P. Moreira;P. Alvarez;J. Serrano;Izzat Darwezeh;T. Wlostowski
中科院分区：
文献类型：
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作者：
P. Moreira;P. Alvarez;J. Serrano;Izzat Darwezeh;T. Wlostowski
提出了一种双混频器时间差（DMTD）的数字结构。这种架构与其他相位频率检测器相比具有几个优点，例如是线性的，没有死区，精度在亚皮秒范围内。所有定时信号中存在的固有相位噪声是限制该相位频率检测器精度的主要原因。因此，本文描述了所提出的架构的优点和缺点，以及它的性能如何变化的时钟相位噪声，通过显示一些实验测量。这种结构的应用，为使用以太网作为数据和同步网络，也进行了讨论。
A digital architecture for the Dual Mixer Time Difference (DMTD) is presented. This architecture has several advantages over other phase frequency detectors such as being linear, not having a dead zone and with an accuracy within the sub-picoseconds range. The intrinsic phase noise present in all timing signals is the main cause of the limitation in the accuracy of this phase frequency detector. Therefore, this paper describes the advantages and disadvantages of the presented architecture as well as how its performance changes with the clock phase noise by showing some experimental measurements. The application of this architecture, for the use of Ethernet as both data and synchronization network, is also discussed.