A performance-driven placement tool for analog integrated circuits
A performance-driven placement tool for analog integrated circuits
复制标题
DOI：
10.1109/4.391116
复制
发表时间：
1995-07
期刊：
影响因子：
--
通讯作者：
K. Lampaert;G. Gielen;W. Sansen
中科院分区：
文献类型：
--
作者：
K. Lampaert;G. Gielen;W. Sansen
本文提出了一种以性能为导向的模拟集成电路布局新方法。放置器件的自由被用来将布局引起的性能降级控制在设计者的规格施加的裕度内。这保证了所得到的布局在结构上将符合所有规格。在模拟退火法的每一次迭代过程中，根据中间解的几何性质计算布局引起的性能降级。布局工具固有地处理对称约束、电路加载效应和器件失配。通过实际电路实例验证了该方法的可行性。>；
This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples. >