A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization

A Dynamic Programming-Based, Path Balancing Technology Mapping Algorithm Targeting Area Minimization
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基于动态规划的路径平衡技术映射算法目标区域最小化

DOI:
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发表时间:
2019
期刊:
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子:
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通讯作者:
M. Pedram
M. Pedram
中科院分区:
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文献类型:
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作者:
G. Pasandi;M. Pedram

文献摘要

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路径平衡技术映射是一种将电路的技术无关逻辑描述(如布尔网络)映射到技术相关门级网表的方法。对于由路径平衡映射器生成的门级网表,电路中的最长路径和最短路径的长度之间的差被最小化。为了实现全路径平衡,可能需要在信号路径上添加缓冲器,在这种情况下,必须适当考虑缓冲器的成本。本文提出了一种基于动态规划的工艺映射算法,该算法生成的最小面积映射解决方案,保证是完全路径平衡的。完全路径平衡映射解是传统的双量子单通量量子电路的基本解,否则将失效。平衡映射解决方案在CMOS电路中也是有用的,以避免(或最小化)不想要的危险活动和由此产生的浪费的动态功耗,以及在波流水线电路中实现最大吞吐量。实验结果表明,我们的路径平衡技术映射算法减少了总面积,静态功耗,路径平衡开销的单通量量子电路的大因素。例如,与最先进的技术映射器相比,它将电路面积减少了111%,平均减少了26.3%。
Path balancing technology mapping is a method of mapping a technology-independent logical description of a circuit, such as a Boolean network, into a technology-dependent, gate-level netlist. For a gate-level netlist generated by the path balancing mapper, the difference between lengths of the longest and the shortest paths in the circuit is minimized. To achieve full path balancing, it may be necessary to add buffers on signal paths, and in such a case, the cost of buffers must be properly accounted for. This paper presents a dynamic programming-based technology mapping algorithm that generates a minimum-area mapping solution which is guaranteed to be fully path balanced. The fully path balanced mapping solution is essential to conventional superconductive single flux quantum circuits, which will fail otherwise. The balanced mapping solution is also useful in CMOS circuits to avoid (or minimize) unwanted hazard activity and the resulting wasteful dynamic power dissipation as well as to achieve the maximum throughput in a wave-pipelined circuit. Experimental results show that our path balancing technology mapping algorithm decreases total area, static power consumption, and path balancing overhead of single flux quantum circuits by large factors. For example, it reduces the circuit area by up to 111% and by an average of 26.3% compared to state-of-the-art technology mappers.