Estimating performance penalty for various fault-tolerant techniques in multicore processors
Estimating performance penalty for various fault-tolerant techniques in multicore processors
复制标题
估计多核处理器中各种容错技术的性能损失
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
A. Napieralski
中科院分区：
文献类型：
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作者：
P. Zając;A. Napieralski
在当前的处理器中，提高计算性能的主要趋势是在芯片上增加越来越多的核。目前，市场上已经有了带有多个核心的处理器，一些研究人员预测，在不久的将来，芯片上会有十分之一甚至数百个核心。另一方面，工艺变化的影响越来越大，将导致更高的故障概率，这可能成为制造商的主要问题。人们可能会怀疑，很快，制造商和设计者将不得不接受部分有缺陷的处理器，并使用容错技术来保证可靠的芯片运行。在本文中，我们研究了故障对多核处理器性能的影响，假设检测到故障核或片上路由器，并根据适当的容错机制对其进行修复、替换或禁用。我们分析了各种容错技术，并对一个4×4网格多核处理器进行了仿真，以量化其性能损失。
The major trend to increase the computing performance in current processors is based on adding more and more cores on chip. Currently, processors with several cores are already available on the market and some researchers predict tenths or even hundreds cores on chip in the near future. On the other hand, the rising impact of process variations will lead to higher probability of faults which may become a major problem for manufacturers. One may suspect that soon manufacturers and designers will have to accept partially defective processors and use fault-tolerance techniques to guarantee a dependable chip operation. In this paper we investigate the impact of faults on multicore processor performance under the assumption that a faulty core or router on chip is detected and either repaired, replaced or disabled, according to appropriate fault-tolerant mechanism. We analyze various fault-tolerant techniques and simulate a 4×4 mesh multicore processor to quantify the performance penalty.