Automated circuit elaboration from incomplete architectural descriptions
Automated circuit elaboration from incomplete architectural descriptions
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根据不完整的架构描述自动阐述电路
DOI：
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发表时间：
2013
期刊：
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通讯作者：
P. Ienne
中科院分区：
文献类型：
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作者：
Andrew Becker;D. Novo;P. Ienne
算术电路是一些最常见的电路，然而为这些电路构建生成器通常既是即席的，也是容易出错的。通常，生成器设计者不直接使用寄存器传输语言，而是使用脚本语言(例如，Perl)来生成RTL，并克服典型RTL语言的有限表现力。我们提出了一种新的生成器构造方法，其中设计语言是自然的和有表现力的，并且为设计人员提供了特殊的设施来减少典型的错误来源。这是建立在以前的工作基础上的，在以前的工作中，设计师写出一个不完整的设计(草图)并提供一个功能参考；然后综合一个完整的、正确的设计。值得注意的是，我们用一种专门为算术生成器量身定做的方法来解决一般情况下的可扩展性问题：随着生成器参数增长生成电路的大小，会逐渐发现插入设计中的不确定性令人满意的值。这种方法大大减少了求解时间，有时比NAı策略快25倍。
Arithmetic circuits are some of the most common circuits, yet building generators for these circuits is usually both ad-hoc and error-prone. Often, generator designers do not directly use Register Transfer Languages, but instead use scripting languages (e.g., Perl) to generate RTL and overcome the limited expressivity of typical RTL languages. We present a new approach to generator construction, where the design language is natural and expressive, and designers are provided with special facilities to alleviate typical sources of errors. This builds on previous work, where designers write an incomplete design (a sketch) and provide a functional reference; a complete, correct design is then synthesized. Notably, we address scalability problems in the general case with an approach tailored specifically for arithmetic generators: satisfying values for the uncertainties inserted in the designs are discovered incrementally as the generator parameters grow the size of the generated circuits. This approach results in significantly reduced solution times, sometimes up to 25 times faster than the naı”ve strategy.