Integration of $\hbox{LaLuO}_{3} \ (\kappa \sim \hbox{30})$ as High-$\kappa$ Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process
Integration of $\hbox{LaLuO}_{3} \ (\kappa \sim \hbox{30})$ as High-$\kappa$ Dielectric on Strained and Unstrained SOI MOSFETs With a Replacement Gate Process
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DOI：
10.1109/led.2010.2089423
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发表时间：
2011
影响因子：
4.9
通讯作者：
E. D. Özben;J. Lopes;A. Nichau;M. Schnee;S. Lenk;A. Besmehn;K. Bourdelle;Q. Zhao;J. Schubert;S. Mantl
中科院分区：
文献类型：
--
作者：
E. D. Özben;J. Lopes;A. Nichau;M. Schnee;S. Lenk;A. Besmehn;K. Bourdelle;Q. Zhao;J. Schubert;S. Mantl
集成的镧镥氧化物（LaLuO 3）与n值为30，第一次，证明了应变和非应变SOI n/p-MOSFET作为栅极介质与完全替代栅极工艺。在LaLuO 3/Si界面上存在一个很薄的SiO2/SiO2过渡层，其Dit能级为4.5 × 1011（eV ·cm 2）-1。具有LaLuO 3/TiN栅极叠层的全耗尽n/p-MOSFET表现出非常好的性能，具有约70 mV/dec的陡峭亚阈值斜率和高Ion/Ioff比。此外，应变SOI显示出增强的电子迁移率与SOI相比的1.7倍。SOI上LaLuO 3的电子和空穴迁移率与报道的Hf基高κ器件中的迁移率相似。
The integration of lanthanum lutetium oxide (LaLuO3) with a n value of 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as a gate dielectric with a full replacement gate process. The LaLuO3/Si interface showed a very thin silicate/SiO2 interlayer with a Dit level of 4.5 × 1011 (eV · cm2)-1. Fully depleted n/p-MOSFETs with LaLuO3/TiN gate stacks indicated very good performance with steep subthreshold slopes of ~70 mV/dec and high Ion/Ioff ratios. In addition, strained SOI shows enhanced electron mobilities with a factor of 1.7 compared to SOI. Both electron and hole mobilities for LaLuO3 on SOI are similar to the mobilities in reported Hf-based high-κ devices.