Instruction-based delay fault self-testing of processor cores
Instruction-based delay fault self-testing of processor cores
复制标题
基于指令的处理器内核延迟故障自检
DOI：
10.1109/icvd.2004.1261051
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
H. Fujiwara
中科院分区：
文献类型：
--
作者：
Virendra Singh;M. Inoue;K. Saluja;H. Fujiwara
提出了一种利用处理器指令集进行延迟故障测试的有效方法。这些测试向量可以应用于功能操作模式，因此，处理器核的自测试成为可能。采用路径延迟故障模型。所提出的方法使用一个图论模型（表示为一个指令执行图）的数据路径和一个有限状态机模型的控制器，用于消除功能上不可测试的路径在早期阶段，而不看电路的细节和提取的约束条件的路径，可以潜在地进行测试。Parwan处理器被用来证明我们的方法的有效性。
This paper proposes an efficient methodology of delay fault testing of processor cores using its instruction set. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible. Path delay fault model is used. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan processor is used to demonstrate the effectiveness of our method.