Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
复制标题
基于 FPGA 的动态可重配置平台中的自适应电压调节
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
J. Núñez
中科院分区：
文献类型：
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作者：
A. Nabina;J. Núñez
功率是限制现场可编程门阵列（FPGA）的适用性的重要问题，因为它被认为比ASIC高一个数量级。最近，FPGA中的动态重新配置已经成为一种可行的技术，能够通过在运行时时分复用所需的功能来实现功耗和成本降低。在本文中，自适应电压调节（AVS）对FPGA的适用性与逻辑和时钟管理资源的动态重新配置一起被考虑，以进一步改善这些器件的功耗曲线。AVS是ASIC中一种流行的节能技术，使器件能够根据工作负载、制造和工作条件调节自己的电压和频率。由此产生的处理平台利用可用的应用程序相关的时序裕度，以实现功率降低高达85%的操作在0.58伏与操作在1伏的标称电压相比。结果还表明，在0.58伏的能量需求是约五倍低于标称电压，这可以解释的静态能量与电压的近似立方关系和事实，即静态组件占主导地位的功耗在考虑FPGA设备。
Power is an important issue limiting the applicability of Field Programmable Gate Arrays (FPGAs) since it is considered to be up to one order of magnitude higher than in ASICs. Recently, dynamic reconfiguration in FPGAs has emerged as a viable technique able to achieve power and cost reductions by time-multiplexing the required functionality at runtime. In this article, the applicability of Adaptive Voltage Scaling (AVS) to FPGAs is considered together with dynamic reconfiguration of logic and clock management resources to further improve the power profile of these devices. AVS is a popular power-saving technique in ASICs that enables a device to regulate its own voltage and frequency based on workload, fabrication, and operating conditions. The resulting processing platform exploits the available application-dependent timing margins to achieve a power reduction up to 85% operating at 0.58 volts compared with operating at a nominal voltage of 1 volt. The results also show that the energy requirements at 0.58 volts are aproximately five times lower compared with nominal voltage and this can be explained by the approximate cubic relation of static energy with voltage and the fact that the static component dominates power consumption in the considered FPGA devices.