Modeling intrinsic fluctuations in decananometer MOS devices due to gate line edge roughness (LER)
Modeling intrinsic fluctuations in decananometer MOS devices due to gate line edge roughness (LER)
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对由于栅极线边缘粗糙度 (LER) 引起的十纳米 MOS 器件的固有波动进行建模
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
Mahmudur Rahman
中科院分区：
文献类型：
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作者：
N. Gunther;E. Hamadeh;D. Niemann;I. Pesic;Mahmudur Rahman
诸如栅极LER的制造工艺所固有的管芯内随机波动结果引起器件特性的相应波动。对于沟道长度小于50 nm的器件，这些波动变得显著，特征尺寸迅速接近实际兴趣。在这个尺度上，界面附近的边缘电场和电荷限制在确定MOS器件特性及其波动中起主导作用。在这项工作中，我们首先表征LER作为一个对数正态概率密度函数（pdf）的空间频率。然后，我们应用三维量子力学修正变分原理（VQM），获得封闭形式的表达式的阈值电压和器件电容的标准偏差由于LER。我们的方法提供了一个简单的物理为基础的替代目前可用的TCAD模拟调查这些复杂的问题作为栅极尺寸，氧化层厚度和沟道掺杂水平的函数。
Intra-die random fluctuation outcomes inherent to fabrication processes such as gate LER give rise to corresponding fluctuations in device characteristics. These fluctuations become significant for devices with channel length less than 50 nm, a feature size rapidly approaching practical interest. At this scale, the fringe electric field and the charge confinement near the interface play dominant roles in determining MOS device properties and their fluctuations. In this work, we first characterize LER as a lognormal probability density function (pdf) in spatial frequency. Then we apply a 3D quantum mechanically corrected variational principle (VQM) to obtain closed-form expressions for standard deviation of threshold voltage and device capacitance due to LER. Our approach provides a simple physics based alternative to the presently available TCAD simulation for investigating these complex issues as functions of gate size, oxide thickness, and channel doping level.