Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
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DOI：
10.1587/transinf.e96.d.1632
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发表时间：
2012-09
期刊：
影响因子：
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通讯作者：
Y. Komatsu;M. Hariyama;M. Kameyama
中科院分区：
文献类型：
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作者：
Y. Komatsu;M. Hariyama;M. Kameyama
总结 本文提出了一种新颖的异步 FPGA 架构，用于基于握手组件的设计。基于握手组件的设计因其易于理解而适用于大规模、复杂的异步电路。本文提出了一种适用于基于握手组件的异步电路的节省空间的 FPGA 架构。此外，由于数据路径可在 FPGA 中编程，因此采用四相双轨编码来构造对延迟变化具有鲁棒性的电路。基于所提出架构的 FPGA 采用 65nm 工艺实现。其评价结果显示
SUMMARY This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshakecomponent-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an areaefficient architecture of an FPGA that is suitable for handshake-componentbased asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65nm process. Its evaluation results show