Register allocation for software pipelined loops
Register allocation for software pipelined loops
复制标题
软件流水线循环的寄存器分配
DOI：
10.1145/143095.143141
复制
发表时间：
1992
期刊：
影响因子：
--
通讯作者：
M. Schlansker
中科院分区：
文献类型：
--
作者：
B. R. Rau;Meng Lee;P. Tirumalai;M. Schlansker
软件流水线是一种重要的指令调度技术，它可以有效地重叠循环的连续迭代并并行执行。本文研究了软件流水线循环的寄存器分配任务，包括有和没有专门用于支持软件流水线的硬件特性。软件管道的寄存器分配提出了一些新问题，导致了非常规的解决方案，特别是在硬件支持的情况下。本文阐述了这些新问题，并提出了一些可供选择的解决策略。这些替代方案经过了一千多个循环的全面测试，以确定最佳的寄存器分配策略，无论是否支持软件流水线的硬件。
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. This paper studies the task of register allocation for software pipelined loops, both with and without hardware features that are specifically aimed at supporting software pipelines. Register allocation for software pipelines presents certain novel problems leading to unconventional solutions, especially in the presence of hardware support. This paper formulates these novel problems and presents a number of alternative solution strategies. These alternatives are comprehensively tested against over one thousand loops to determine the best register allocation strategy, both with and without the hardware support for software pipelining.