GALS Design for Spectral Peak Attenuation of Switching Current
GALS Design for Spectral Peak Attenuation of Switching Current
复制标题
开关电流频谱峰值衰减的 GALS 设计
DOI：
10.1109/async.2013.28
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发表时间：
2013
期刊：
影响因子：
--
通讯作者：
E. Grass
中科院分区：
文献类型：
--
作者：
Xin Fan;O. Schrape;M. Marinkovic;Peter Dahnert;M. Krstic;E. Grass
当数字电路与全局时钟同步时，常常会受到开关噪声的影响。这项工作通过应用全局异步局部同步（GALS）设计来研究开关电流的频谱峰值衰减。理论上证明，特别是对于具有 M 个时钟域的准同步设计，在时钟频率的低阶谐波下可以实现高达 20logM dB 的衰减。功耗平衡 GALS 划分被发现对于频谱噪声衰减来说是首选，因为它提供了针对各个块中当前形状变化的鲁棒性。已经在130 nm CMOS同步/GALS双核FMCW-RADAR芯片（名为Lighthouse）上进行了实验。与同步设计相比，在片上电源上，对于具有五个准同步时钟的功率平衡GALS设计，在基本时钟频率处可以测量到12.29dB的频谱峰值衰减。
Digital circuits often suffer from the switching noise when synchronized by a global clock. This work investigates the spectral peak attenuation of the switching current by applying Globally Asynchronous Locally Synchronous (GALS) design. It is theoretically proven that, in particular for a plesiochronous design with M clock domains, an attenuation of up to 20logM dB can be achieved at lower order harmonics of the clock frequency. Power-consumption balanced GALS partitioning is found to be preferred for spectral noise attenuation, since it provides robustness against the current shape variations in individual blocks. Experiments on a 130-nm CMOS synchronous/GALS dual-core FMCW-RADAR chip, named Lighthouse, have been performed. Comparing with the synchronous design, on the on-chip power supply, a spectral peak attenuation of 12.29 dB at the fundamental clock frequency can be measured for the power balanced GALS design with five plesio-chronous clocks.