Automated transistor sizing for FPGA architecture exploration
Automated transistor sizing for FPGA architecture exploration
复制标题
用于 FPGA 架构探索的自动晶体管尺寸调整
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
Jonathan Rose
中科院分区：
文献类型：
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作者：
Ian Kuon;Jonathan Rose
创建一个FPGA需要广泛的晶体管级设计。这对于最终设计和体系结构探索都是必要的，因为要考虑许多不同的逻辑和路由体系结构。对于这样的探索，在晶体管级设计上花费大量的时间是不可行的。本文提出了一种用于现场可编程门阵列结构探索的晶体管自动调整工具，该工具采用两阶段的方法--先用简单的建模进行粗略的快速阶段，然后用精确得多的模型进行细化。该系统的输出是针对特定的面积延迟标准进行优化的设计。我们将我们的结果质量与以前的手动和部分自动方法进行比较。此外，我们的工具已被用于生成数百个候选架构，我们将发布这些架构以支持未来的高质量探索。
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and routing architectures are considered. For such explorations, it is not feasible to spend significant amounts of time on transistor-level design. This paper presents an automated transistor sizing tool for FPGA architecture exploration that uses a two-phased approach - a coarse rapid phase with simple modeling followed by refinement with much more accurate models. The output of the system is a design optimized towards a specific area-delay criterion. We compare the quality of our results to prior manual and partially automated approaches. Also, our tool has been used to produce hundreds of candidate architectures which we are releasing to support future high quality explorations.